URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] - Rev 57

Rev	Log message	Author	Age	Path
36	no message	mohor	8315d 06h	/uart16550/tags/asyst_3/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8317d 00h	/uart16550/tags/asyst_3/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8318d 23h	/uart16550/tags/asyst_3/rtl/verilog/
33	Small synopsis fixes	gorban	8328d 06h	/uart16550/tags/asyst_3/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8328d 23h	/uart16550/tags/asyst_3/rtl/verilog/
31	small fix	gorban	8329d 19h	/uart16550/tags/asyst_3/rtl/verilog/
30	Modified port names again	gorban	8384d 00h	/uart16550/tags/asyst_3/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8384d 19h	/uart16550/tags/asyst_3/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8385d 07h	/uart16550/tags/asyst_3/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8386d 00h	/uart16550/tags/asyst_3/rtl/verilog/