URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 56

Rev	Log message	Author	Age	Path
35	Fixes to break and timeout conditions	gorban	8317d 02h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8319d 01h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8328d 08h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8329d 01h	/uart16550/trunk/rtl/verilog/
31	small fix	gorban	8329d 21h	/uart16550/trunk/rtl/verilog/
30	Modified port names again	gorban	8384d 02h	/uart16550/trunk/rtl/verilog/
29	Things connected to parity changed. Clock devider changed.	mohor	8384d 21h	/uart16550/trunk/rtl/verilog/
28	FIFO was not cleared after the data was read bug fixed.	mohor	8385d 09h	/uart16550/trunk/rtl/verilog/
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8386d 02h	/uart16550/trunk/rtl/verilog/