URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 62

Rev	Log message	Author	Age	Path
42	ti_int_pnd error fixed.	mohor	8282d 20h	/uart16550/trunk/rtl/verilog/
41	ti_int_d error fixed.	mohor	8282d 20h	/uart16550/trunk/rtl/verilog/
40	Synthesis bugs fixed. Some other minor changes	gorban	8284d 22h	/uart16550/trunk/rtl/verilog/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8286d 20h	/uart16550/trunk/rtl/verilog/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8287d 17h	/uart16550/trunk/rtl/verilog/
36	no message	mohor	8293d 01h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8294d 19h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8296d 18h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8306d 01h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8306d 18h	/uart16550/trunk/rtl/verilog/