URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 63

Rev	Log message	Author	Age	Path
43	lsr1r error fixed.	mohor	8277d 08h	/uart16550/trunk/rtl/verilog/
42	ti_int_pnd error fixed.	mohor	8277d 08h	/uart16550/trunk/rtl/verilog/
41	ti_int_d error fixed.	mohor	8277d 08h	/uart16550/trunk/rtl/verilog/
40	Synthesis bugs fixed. Some other minor changes	gorban	8279d 10h	/uart16550/trunk/rtl/verilog/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8281d 08h	/uart16550/trunk/rtl/verilog/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8282d 05h	/uart16550/trunk/rtl/verilog/
36	no message	mohor	8287d 13h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8289d 07h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8291d 06h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8300d 13h	/uart16550/trunk/rtl/verilog/