URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 65

Rev	Log message	Author	Age	Path
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8247d 18h	/uart16550/trunk/rtl/verilog/
44	fixed more typo bugs	gorban	8261d 18h	/uart16550/trunk/rtl/verilog/
43	lsr1r error fixed.	mohor	8262d 01h	/uart16550/trunk/rtl/verilog/
42	ti_int_pnd error fixed.	mohor	8262d 01h	/uart16550/trunk/rtl/verilog/
41	ti_int_d error fixed.	mohor	8262d 01h	/uart16550/trunk/rtl/verilog/
40	Synthesis bugs fixed. Some other minor changes	gorban	8264d 03h	/uart16550/trunk/rtl/verilog/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8266d 01h	/uart16550/trunk/rtl/verilog/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8266d 22h	/uart16550/trunk/rtl/verilog/
36	no message	mohor	8272d 06h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8274d 00h	/uart16550/trunk/rtl/verilog/