URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 87

Rev	Log message	Author	Age	Path
58	After reset modem status register MSR should be reset.	mohor	8245d 14h	/uart16550/trunk/rtl/verilog/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8246d 13h	/uart16550/trunk/rtl/verilog/
56	thre irq should be cleared only when being source of interrupt.	mohor	8246d 14h	/uart16550/trunk/rtl/verilog/
55	some synthesis bugs fixed	gorban	8247d 02h	/uart16550/trunk/rtl/verilog/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8247d 15h	/uart16550/trunk/rtl/verilog/
53	Scratch register define added.	mohor	8248d 15h	/uart16550/trunk/rtl/verilog/
52	Scratch register added	gorban	8249d 04h	/uart16550/trunk/rtl/verilog/
51	Igor fixed break condition bugs	gorban	8249d 04h	/uart16550/trunk/rtl/verilog/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8253d 09h	/uart16550/trunk/rtl/verilog/
49	committed the debug interface file	gorban	8255d 03h	/uart16550/trunk/rtl/verilog/