URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 100

Rev	Log message	Author	Age	Path
80		mikaeljf	5108d 11h	/versatile_mem_ctrl/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5146d 00h	/versatile_mem_ctrl/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5148d 07h	/versatile_mem_ctrl/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5156d 06h	/versatile_mem_ctrl/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5161d 07h	/versatile_mem_ctrl/
75		mikaeljf	5161d 08h	/versatile_mem_ctrl/
74	Minor update of rtl Makefile.	mikaeljf	5165d 07h	/versatile_mem_ctrl/
73	Minor updates to fix lost revisions 69 and 70.	mikaeljf	5165d 08h	/versatile_mem_ctrl/
72	Restored lost revisions 69 and 70.	mikaeljf	5165d 09h	/versatile_mem_ctrl/
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5165d 09h	/versatile_mem_ctrl/