URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 103

Rev	Log message	Author	Age	Path
83		mikaeljf	5114d 13h	/versatile_mem_ctrl/
82		mikaeljf	5114d 17h	/versatile_mem_ctrl/
81		mikaeljf	5115d 14h	/versatile_mem_ctrl/
80		mikaeljf	5115d 15h	/versatile_mem_ctrl/
79	Added defines that fix bugs with slow wishbone clocks doing burst writes	julius	5153d 05h	/versatile_mem_ctrl/
78	Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun	julius	5155d 12h	/versatile_mem_ctrl/
77	SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16	julius	5163d 10h	/versatile_mem_ctrl/
76	Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now	julius	5168d 11h	/versatile_mem_ctrl/
75		mikaeljf	5168d 12h	/versatile_mem_ctrl/
74	Minor update of rtl Makefile.	mikaeljf	5172d 11h	/versatile_mem_ctrl/