URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 54

Rev	Log message	Author	Age	Path
34	added	unneback	5263d 16h	/versatile_mem_ctrl/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5263d 18h	/versatile_mem_ctrl/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5266d 22h	/versatile_mem_ctrl/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5268d 15h	/versatile_mem_ctrl/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5268d 15h	/versatile_mem_ctrl/
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5272d 15h	/versatile_mem_ctrl/
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5272d 17h	/versatile_mem_ctrl/
27		unneback	5276d 08h	/versatile_mem_ctrl/
26	compiles OK, not simulated	unneback	5278d 07h	/versatile_mem_ctrl/
25		unneback	5278d 10h	/versatile_mem_ctrl/