URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] - Rev 86

Rev	Log message	Author	Age	Path
66		unneback	5169d 17h	/versatile_mem_ctrl/
65	added	unneback	5169d 17h	/versatile_mem_ctrl/
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5170d 16h	/versatile_mem_ctrl/
63	Fixed a couple of sdr_16 bugs to do with tracking of opened banks	julius	5171d 00h	/versatile_mem_ctrl/
62	Added note to sdr_16_defines.v asking if it's still used	julius	5171d 02h	/versatile_mem_ctrl/
61	Fixed blocking/nonblocking assign issue in sdr_16 fsm	julius	5175d 00h	/versatile_mem_ctrl/
60	Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation.	julius	5175d 00h	/versatile_mem_ctrl/
59	counter changed to shift register	unneback	5175d 02h	/versatile_mem_ctrl/
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5176d 03h	/versatile_mem_ctrl/
57	added support for early termination of burst access	unneback	5177d 05h	/versatile_mem_ctrl/