URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] - Rev 36

Rev	Log message	Author	Age	Path
16	Added fizzim.pl	mikaeljf	5265d 22h	/versatile_mem_ctrl/trunk/
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5266d 23h	/versatile_mem_ctrl/trunk/
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5357d 01h	/versatile_mem_ctrl/trunk/
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5357d 04h	/versatile_mem_ctrl/trunk/
12	Minor update of whishbone FSMs in TB	mikaeljf	5367d 04h	/versatile_mem_ctrl/trunk/
11	Initial version with support for DDR	mikaeljf	5367d 16h	/versatile_mem_ctrl/trunk/
10		unneback	5395d 00h	/versatile_mem_ctrl/trunk/
9	testbench	unneback	5395d 00h	/versatile_mem_ctrl/trunk/
8		unneback	5490d 20h	/versatile_mem_ctrl/trunk/
7		unneback	5490d 21h	/versatile_mem_ctrl/trunk/