URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 102

Rev	Log message	Author	Age	Path
71	Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes	julius	5225d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/
70		mikaeljf	5229d 06h	/versatile_mem_ctrl/trunk/rtl/verilog/
69		mikaeljf	5230d 02h	/versatile_mem_ctrl/trunk/rtl/verilog/
68	cleaqnup	unneback	5231d 14h	/versatile_mem_ctrl/trunk/rtl/verilog/
67	added FSM for wb if	unneback	5231d 15h	/versatile_mem_ctrl/trunk/rtl/verilog/
66		unneback	5231d 17h	/versatile_mem_ctrl/trunk/rtl/verilog/
65	added	unneback	5231d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/
64	Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file	julius	5232d 17h	/versatile_mem_ctrl/trunk/rtl/verilog/
63	Fixed a couple of sdr_16 bugs to do with tracking of opened banks	julius	5233d 00h	/versatile_mem_ctrl/trunk/rtl/verilog/
62	Added note to sdr_16_defines.v asking if it's still used	julius	5233d 02h	/versatile_mem_ctrl/trunk/rtl/verilog/