URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 60

Rev	Log message	Author	Age	Path
39	updated FIFO and SDR 16	unneback	5237d 01h	/versatile_mem_ctrl/trunk/rtl/verilog/
38	casex in rw state to save logic	unneback	5239d 09h	/versatile_mem_ctrl/trunk/rtl/verilog/
37		unneback	5239d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/
36		unneback	5240d 00h	/versatile_mem_ctrl/trunk/rtl/verilog/
35	work for limited test case	unneback	5240d 07h	/versatile_mem_ctrl/trunk/rtl/verilog/
34	added	unneback	5240d 07h	/versatile_mem_ctrl/trunk/rtl/verilog/
33	work for limited test case, no cke inhibit for fifo empty	unneback	5240d 10h	/versatile_mem_ctrl/trunk/rtl/verilog/
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5243d 13h	/versatile_mem_ctrl/trunk/rtl/verilog/
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5245d 07h	/versatile_mem_ctrl/trunk/rtl/verilog/
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5245d 07h	/versatile_mem_ctrl/trunk/rtl/verilog/