URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 80

Rev	Log message	Author	Age	Path
60	Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation.	julius	5250d 21h	/versatile_mem_ctrl/trunk/rtl/verilog/
59	counter changed to shift register	unneback	5250d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/
58	sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm	julius	5252d 00h	/versatile_mem_ctrl/trunk/rtl/verilog/
57	added support for early termination of burst access	unneback	5253d 02h	/versatile_mem_ctrl/trunk/rtl/verilog/
56	corrected fifo_rd_data in state w4d	unneback	5254d 19h	/versatile_mem_ctrl/trunk/rtl/verilog/
55	Fixed up sdr16 dqm output	julius	5255d 14h	/versatile_mem_ctrl/trunk/rtl/verilog/
54	dqm moved into FSM	unneback	5256d 11h	/versatile_mem_ctrl/trunk/rtl/verilog/
53		unneback	5256d 11h	/versatile_mem_ctrl/trunk/rtl/verilog/
52	act exit for read updated	unneback	5257d 13h	/versatile_mem_ctrl/trunk/rtl/verilog/
51	act exit for read updated	unneback	5257d 13h	/versatile_mem_ctrl/trunk/rtl/verilog/