URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [rtl/] [verilog/] - Rev 62

Rev	Log message	Author	Age	Path
17	Major rework. Included generic memory models. Core now supports pixel clocks at same speed as wishbone clock (except for 8bpp color mode)	rherveille	8332d 21h	/vga_lcd/trunk/rtl/verilog/
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8360d 03h	/vga_lcd/trunk/rtl/verilog/