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Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5207d 00h /xgate/
58 WISHBONE Bus update. rehayes 5259d 00h /xgate/
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5259d 03h /xgate/
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5275d 04h /xgate/
55 Minor change to instruction set details. rehayes 5275d 04h /xgate/
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5275d 04h /xgate/
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5275d 04h /xgate/
52 Minor changes to aide waveform debug rehayes 5275d 04h /xgate/
51 Corrections to ADC and SBC instructions, First pass at documentaion instruction set details rehayes 5291d 00h /xgate/
50 incremental update to match status bit changes rehayes 5291d 00h /xgate/

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