URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] - Rev 80

Rev	Log message	Author	Age	Path
60	Add ability at insert wait states on RAM access	rehayes	5230d 03h	/xgate/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5230d 03h	/xgate/
58	WISHBONE Bus update.	rehayes	5282d 02h	/xgate/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5282d 05h	/xgate/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5298d 06h	/xgate/
55	Minor change to instruction set details.	rehayes	5298d 06h	/xgate/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5298d 06h	/xgate/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5298d 06h	/xgate/
52	Minor changes to aide waveform debug	rehayes	5298d 06h	/xgate/
51	Corrections to ADC and SBC instructions, First pass at documentaion instruction set details	rehayes	5314d 02h	/xgate/