URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] - Rev 81

Rev	Log message	Author	Age	Path
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5215d 10h	/xgate/
60	Add ability at insert wait states on RAM access	rehayes	5215d 10h	/xgate/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5215d 10h	/xgate/
58	WISHBONE Bus update.	rehayes	5267d 10h	/xgate/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5267d 13h	/xgate/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5283d 14h	/xgate/
55	Minor change to instruction set details.	rehayes	5283d 14h	/xgate/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5283d 14h	/xgate/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5283d 14h	/xgate/
52	Minor changes to aide waveform debug	rehayes	5283d 14h	/xgate/