URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] - Rev 82

Rev	Log message	Author	Age	Path
62	Cleanup implicit wire declarations.	rehayes	5222d 11h	/xgate/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5229d 11h	/xgate/
60	Add ability at insert wait states on RAM access	rehayes	5229d 11h	/xgate/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5229d 11h	/xgate/
58	WISHBONE Bus update.	rehayes	5281d 11h	/xgate/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5281d 14h	/xgate/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5297d 14h	/xgate/
55	Minor change to instruction set details.	rehayes	5297d 14h	/xgate/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5297d 15h	/xgate/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5297d 15h	/xgate/