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[/] [xgate/] - Rev 88

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Rev Log message Author Age Path
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5169d 22h /xgate/
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5169d 22h /xgate/
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5189d 18h /xgate/
65 Parameterize delays based on number of RAM wait states. rehayes 5189d 18h /xgate/
64 Fixed more bugs related to wait states and debug mode. rehayes 5189d 18h /xgate/
63 Remove historical output ports that are no longer used. rehayes 5199d 18h /xgate/
62 Cleanup implicit wire declarations. rehayes 5199d 18h /xgate/
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5206d 17h /xgate/
60 Add ability at insert wait states on RAM access rehayes 5206d 18h /xgate/
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5206d 18h /xgate/

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