URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] - Rev 82

Rev	Log message	Author	Age	Path
62	Cleanup implicit wire declarations.	rehayes	5199d 23h	/xgate/trunk/
61	Update to RISC block to fix DEBUG mode, testbench update	rehayes	5206d 23h	/xgate/trunk/
60	Add ability at insert wait states on RAM access	rehayes	5206d 23h	/xgate/trunk/
59	Fix bug in entering DEBUG mode from WB bus command	rehayes	5206d 23h	/xgate/trunk/
58	WISHBONE Bus update.	rehayes	5258d 23h	/xgate/trunk/
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5259d 02h	/xgate/trunk/
56	Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states.	rehayes	5275d 03h	/xgate/trunk/
55	Minor change to instruction set details.	rehayes	5275d 03h	/xgate/trunk/
54	complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.	rehayes	5275d 03h	/xgate/trunk/
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5275d 03h	/xgate/trunk/