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[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 101

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Rev Log message Author Age Path
21 Added timeout, total error count, and XGCHN test rehayes 5425d 00h /xgate/trunk/bench/verilog/
20 Added event signal for compare error tracking in top level test bench. rehayes 5425d 00h /xgate/trunk/bench/verilog/
19 Verilog memory image for testing rehayes 5425d 00h /xgate/trunk/bench/verilog/
11 Update with Single Step debuging test rehayes 5439d 00h /xgate/trunk/bench/verilog/
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5452d 00h /xgate/trunk/bench/verilog/
2 Initial Checkin rehayes 5459d 22h /xgate/trunk/bench/verilog/

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