URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 92

Rev	Log message	Author	Age	Path
29	Added some constant assigments, still needs more work to complete	rehayes	5364d 08h	/xgate/trunk/rtl/verilog/
28	Added comment line	rehayes	5364d 08h	/xgate/trunk/rtl/verilog/
26	Add synopsys commands, add else defaults for semphore state machine.	rehayes	5379d 09h	/xgate/trunk/rtl/verilog/
25	Fix connected net name	rehayes	5379d 09h	/xgate/trunk/rtl/verilog/
24	Delete unused inputs	rehayes	5379d 10h	/xgate/trunk/rtl/verilog/
17	Additions for XGCHID debug commands	rehayes	5385d 08h	/xgate/trunk/rtl/verilog/
15	Fix R1 load at boot up, add debug features	rehayes	5398d 06h	/xgate/trunk/rtl/verilog/
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5399d 08h	/xgate/trunk/rtl/verilog/
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5412d 08h	/xgate/trunk/rtl/verilog/
2	Initial Checkin	rehayes	5420d 06h	/xgate/trunk/rtl/verilog/