URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] - Rev 30

Rev	Log message	Author	Age	Path
10	Changed the name of the memtest.s file.	dgisselq	3212d 12h	/xulalx25soc/
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3212d 12h	/xulalx25soc/
8	Added an interface description to the comments at the top of the file.	dgisselq	3214d 21h	/xulalx25soc/
7	Mostly minor changes. Fixed the legal copyright statement in the UART files, adjusted some comments, and made sure that the zipdbg program contained all the latest features from our Vault.	dgisselq	3214d 22h	/xulalx25soc/
6	Initial file load, likely to be buggy, but the initial load nonetheless.	dgisselq	3215d 08h	/xulalx25soc/
5	Initial software version, in support of the project. At this point, they are provided with no guarantees that they work. (They did use to work--on an older build, but I haven't been able to verify that they work with this newer build yet.)	dgisselq	3215d 08h	/xulalx25soc/
4	Here's an initial, albeit incomplete, build.	dgisselq	3215d 09h	/xulalx25soc/
3		dgisselq	3215d 09h	/xulalx25soc/
2	A very first, albeit incomplete, build.	dgisselq	3215d 09h	/xulalx25soc/
1	The project and the structure was created	root	3215d 10h	/xulalx25soc/