URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] - Rev 38

Rev	Log message	Author	Age	Path
18	Got the bitfile back up to speed at 80 MHz.	dgisselq	3103d 10h	/xulalx25soc/
17	Some basic updates, to include adding in a missing file (zipstate). Most of these updates include making sure that the XuLA2 device can be accessed via the USB. (Prior versions accessed the FPGA via serial port or network ...)	dgisselq	3103d 11h	/xulalx25soc/
16	Updates to allow a test of the ICAP configuration interface.	dgisselq	3103d 11h	/xulalx25soc/
15	WORKING VERSION! ... or, at least the memory test works.	dgisselq	3105d 06h	/xulalx25soc/
14	Quick bug fix.	dgisselq	3105d 06h	/xulalx25soc/
13	This version is now working. (It probably would've worked before, but everything is now working.)	dgisselq	3105d 06h	/xulalx25soc/
12	Modified to match the settings I'm now using within ISE.	dgisselq	3105d 09h	/xulalx25soc/
11	Getting software up and running on the board for the first time. (Not there yet, but I think these items have now proven themselves.)	dgisselq	3105d 09h	/xulalx25soc/
10	Changed the name of the memtest.s file.	dgisselq	3105d 09h	/xulalx25soc/
9	Bug fixes, optimizations, etc. as part of building for an actual hardware implementation. Most notably, the speed was lowered from 80MHz down to 76 MHz.	dgisselq	3105d 09h	/xulalx25soc/