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[/] [xulalx25soc/] - Rev 73

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Rev Log message Author Age Path
53 Added a touch of error checking. dgisselq 3014d 10h /xulalx25soc/
52 This brings the XuLA2-LX25 SoC up to speed with the rest of the ZipCPU, and
prepares it for the 32x32 bit multiply instruction set change.		 dgisselq 3014d 10h /xulalx25soc/
51 Lots of bug fixes. The ugliest were in the prefetch cache, where instructions
from one cache line were being issued as valid in another. Other fixes include
pipeline fixes so that LOD (Rx),Rx; LOD(Rx),Rx works, and more. Finally, the
decode was adjusted so that brev no longer affects the flags.		 dgisselq 3024d 08h /xulalx25soc/
50 Updates to fix some broken early branching code, both in idecode and pfcache. dgisselq 3033d 11h /xulalx25soc/
49 Added some documentation to make the read and write calls easier to understand. dgisselq 3042d 11h /xulalx25soc/
48 Cleaned up the documentation a touch. It no longer reads like the bugs I used
to debug are still being debugged ...		 dgisselq 3044d 13h /xulalx25soc/
47 Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.)		 dgisselq 3044d 13h /xulalx25soc/
46 This is a bug fix release--fixing the bug that kept dumpsdram.cpp/wbsdram.v
from working when long pipelined reads were interrupted by the necessity of
a pair of refresh cycles.		 dgisselq 3044d 13h /xulalx25soc/
45 Minor cosmetic change, eliminates a warning in Xilinx's XISE but offers no
functional difference.		 dgisselq 3048d 08h /xulalx25soc/
44 NELM parameter adjusted to reflect the maximum number of lines the compressed
scope can handle: 31, not 32.		 dgisselq 3048d 08h /xulalx25soc/

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