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Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [sw/] - Rev 118

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Rev Log message Author Age Path
40 This adds to dumpsdram the capability to run over a port, such as with
busmaster_tb.		 dgisselq 2997d 16h /xulalx25soc/trunk/sw/
38 Updated to remove the build dependence upon ZipCPU. dgisselq 2999d 15h /xulalx25soc/trunk/sw/
33 Oops -- the audio was wired audio first then the interrupt controller, not
the other way around. This adjusts regdefs to match what's on the chip.		 dgisselq 3004d 08h /xulalx25soc/trunk/sw/
31 A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25.		 dgisselq 3004d 08h /xulalx25soc/trunk/sw/
30 Bug fixes. In particular, this fixes a segmentation violation. dgisselq 3004d 12h /xulalx25soc/trunk/sw/
29 This adds a vastly updated and superious ziprun capability to the repository.
ziprun now accepts ELF program files *only*, reads them, and places them onto
the board. This includes the ability, within the ELF file, of specifying
whether or not the data is sent to block ram, SD ram, or Flash, as well as
the ability of specifying the initial address. (Of course, that's a one time
thing--to always have the same initial address, set the address in
rtl/busmaster.v)		 dgisselq 3005d 04h /xulalx25soc/trunk/sw/
28 Oops--two files needed by zipdbg weren't originally placed in the directory. dgisselq 3005d 09h /xulalx25soc/trunk/sw/
25 Fixing compile time warnings. dgisselq 3005d 09h /xulalx25soc/trunk/sw/
24 Added the #define necessary to enable (and clear) SCOPE interrupts. dgisselq 3011d 07h /xulalx25soc/trunk/sw/
17 Some basic updates, to include adding in a missing file (zipstate). Most of
these updates include making sure that the XuLA2 device can be accessed via
the USB. (Prior versions accessed the FPGA via serial port or network ...)		 dgisselq 3070d 09h /xulalx25soc/trunk/sw/

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