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47 Added some new graphics, includes the file for the Zip Bones system. dgisselq 3173d 22h /zipcpu/trunk/doc/
39 Here's the documentation update to support the pipelined read/writes of
the bus from the CPU, as well as the test file that proved they worked.		 dgisselq 3177d 01h /zipcpu/trunk/doc/
37 Fixed some minor spelling errors. dgisselq 3185d 17h /zipcpu/trunk/doc/
36 *Lots* of changes to increase processing speed and remove pipeline stalls.

Removed the useless flash cache, replacing it with a proper DMA controller.

"make test" in the main directory now runs a test program in Verilator and
reports on the results.		 dgisselq 3186d 06h /zipcpu/trunk/doc/
35 I updated the system diagram to reflect the new version that has a direct
memory access controller, rather than the (useless) manual cache.		 dgisselq 3202d 21h /zipcpu/trunk/doc/
33 Finally finished a first draft of the full specification! dgisselq 3214d 23h /zipcpu/trunk/doc/
32 Updated the document to match the most recent changes to the CPU. Specifically,
these include the re-instatement of the full SUB command with immediate offset,
and ... others I cannot remember.

The new document also describes what conditions create pipeline stalls,
together with how many cycles each stall condition will create.		 dgisselq 3215d 07h /zipcpu/trunk/doc/
24 Lots more changes to the spec. It's still not done, but it is more complete
than before.		 dgisselq 3218d 08h /zipcpu/trunk/doc/
23 Oops -- left some portions of the RTC Clock spec in with the ZIP CPU spec.
These were quickly removed.		 dgisselq 3220d 04h /zipcpu/trunk/doc/
22 dgisselq 3220d 04h /zipcpu/trunk/doc/

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