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Rev Log message Author Age Path
144 chsnge comp.des to des1 simont 7735d 16h /
143 add wire sub_result, conect it to des_acc and des1. simont 7735d 16h /
142 optimize state machine. simont 7736d 17h /
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7736d 19h /
140 cahnge assigment to pc_wait (remove istb_o) simont 7736d 19h /
139 add aditional alu destination to solve critical path. simont 7737d 13h /
138 Change buffering to save one clock per instruction. simont 7737d 13h /
137 change to fit xrom. simont 7737d 18h /
136 registering outputs. simont 7737d 18h /
135 prepared start of receiving if ren is not active. simont 7743d 17h /

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