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Rev Log message Author Age Path
24 CRC changed so more thorough testing is done. mohor 8300d 07h /
23 Trace disabled by default. mohor 8306d 09h /
22 Register length fixed. mohor 8306d 09h /
21 CRC is returned when chain selection data is transmitted. mohor 8307d 05h /
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8308d 08h /
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8320d 09h /
18 Reset signals are not combined any more. mohor 8322d 18h /
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8346d 07h /
16 bs_chain_o port added. mohor 8348d 07h /
15 bs_chain_o added. mohor 8348d 08h /

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