URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] - Rev 45

Rev	Log message	Author	Age	Path
25	trst signal is synchronized to wb_clk_i.	mohor	8241d 02h	/
24	CRC changed so more thorough testing is done.	mohor	8242d 04h	/
23	Trace disabled by default.	mohor	8248d 06h	/
22	Register length fixed.	mohor	8248d 06h	/
21	CRC is returned when chain selection data is transmitted.	mohor	8249d 02h	/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8250d 05h	/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8262d 05h	/
18	Reset signals are not combined any more.	mohor	8264d 14h	/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8288d 04h	/
16	bs_chain_o port added.	mohor	8290d 04h	/