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Rev Log message Author Age Path
135 Added debug output to synthesizable MPU template. ja_rd 4820d 09h /
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.
ja_rd 4820d 09h /
133 First draft of the SDRAM controller
(Still unused in the code working base)
ja_rd 4823d 07h /
132 Fixed bug in stall logic
(stall for back-to-back SW instructions was wrong)
ja_rd 4823d 07h /
131 change to local system-dependent directory path ja_rd 4823d 07h /
130 typo fix ja_rd 4823d 07h /
129 updated pregenerated demo ('hello') ja_rd 4823d 07h /
128 updated precompiled simulation testbench ja_rd 4823d 07h /
127 added SDRAM verilog simulation model to sim script ja_rd 4823d 07h /
126 added SDRAM verilog simulation model ja_rd 4823d 07h /

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