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Rev Log message Author Age Path
28 Ray Intersection Test, Pipe enable clock. jguarin2002 5392d 16h /
27 GPL License. And comments removed. jguarin2002 5392d 16h /
26 Independent "row through" signals for each cell in the row. jguarin2002 5392d 17h /
25 floor0Row : an entire dot product cell rows. With parameterizable cell numbers. jguarin2002 5392d 17h /
24 Typos...... jguarin2002 5392d 19h /
23 A 1 stage pipe 3 operand simultaneous adder, with parameterizable width. jguarin2002 5392d 20h /
22 Package file declarations :

Declared component for arithmetic functions.
jguarin2002 5392d 20h /
21 A 1 stage minimun distance comparer.

This block turns out to be a collection of instances:

{LT+SCANFFx2}
jguarin2002 5392d 20h /
20 I must check that there are no latches inferred in what I want to be DFF with enable signals.

The 1 stage pipe K comparison cell.
jguarin2002 5392d 20h /
19 Added some control signals.
Added a 3 operands 36 bits adder (12 ns)-> 1 stage pipe.
Added a 18x18 bits multiplier (10 ns) -> 1 stage pipe.
So... the dot cell goes upwards on a two stage pipe:

STAGE1:{M(2,18)P1x3} STAGE2:{A(3,36)P1x1}
jguarin2002 5392d 21h /

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