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Subversion Repositories open8_urisc

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Rev	Log message	Author	Age	Path
171	Fixed comments for offsets 0x0 - 0x3 to indicate the read value	jshamlet	3092d 07h	/
170	Added 24-bit resolution epoch timer / alarm clock	jshamlet	3092d 07h	/
169	Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules.	jshamlet	3147d 08h	/
168	Simplified write data path logic, Converted RTC to packed BCD, Corrected several bugs in real time clock component,	jshamlet	3926d 04h	/
167	Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow. Added several useful modules that use the Open8 bus.	jshamlet	3934d 02h	/
166	fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301	khays	4498d 03h	/
165	fixed issues with PC relative fixups in the linker	khays	4499d 10h	/
164	Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low.	jshamlet	4569d 22h	/
163	sync with binutils 2.22.51.20111114	khays	4607d 10h	/
162	Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set.	jshamlet	4660d 15h	/

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