OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 220

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
200 Renamed dual-port buffer to match other entities. jshamlet 1542d 18h /
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1542d 19h /
198 Removed debugging memory jshamlet 1543d 03h /
197 Fixed incorrect comments jshamlet 1543d 03h /
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1543d 04h /
195 Added dual-port RAM core for SDLC interface. jshamlet 1543d 22h /
194 Cleaned up licensing sections jshamlet 1543d 22h /
193 Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. jshamlet 1543d 23h /
192 Added SDLC packet engine jshamlet 1543d 23h /
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.
jshamlet 1543d 23h /

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.