URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] - Rev 287

Rev	Log message	Author	Age	Path
267	Corrected the file description to indicate this is an example package.	jshamlet	1329d 14h	/
266	Accidentally uploaded incorrect example file for Open8_cfg.vhd	jshamlet	1329d 14h	/
265	Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset.	jshamlet	1421d 23h	/
264	Updated comments	jshamlet	1431d 20h	/
263	Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES. Also separated the SDLC TX and RX interrupts so that they could be handled separately.	jshamlet	1431d 20h	/
262	Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map.	jshamlet	1441d 00h	/
261	Increased delay timer to 7 bits for button press detection.	jshamlet	1448d 00h	/
260	Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations.	jshamlet	1460d 23h	/
259	Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE, Added a pulse interval measurement entity, Fixed comments.	jshamlet	1461d 00h	/
258	Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity.	jshamlet	1461d 22h	/