URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 56

Rev	Log message	Author	Age	Path
36	Remove old core version.	olivier.girard	5289d 22h	/
35	Update documentation to reflect the latest Verilog changes.	olivier.girard	5289d 22h	/
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5289d 23h	/
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5290d 00h	/
32	Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory.	olivier.girard	5291d 20h	/
31	Update documentation (new Altera FPGA project + diverse minor updates)	olivier.girard	5291d 21h	/
30	Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution).	olivier.girard	5291d 21h	/
29	Add Altera Cyclone II FPGA project example.	olivier.girard	5291d 22h	/
28	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5300d 06h	/
27	renamed "diligent_s3board" directory to "xilinx_diligent_s3board"	olivier.girard	5300d 06h	/