URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 392

Rev	Log message	Author	Age	Path
372	Toolchain install script uClibc variable update	julius	5074d 11h	/
371	Toolchain install script binutils commented out fix	julius	5074d 11h	/
370	Toolchain install script uclibc url fix	julius	5074d 11h	/
369	Toolchain build script binutils path fix	julius	5074d 12h	/
368	Toolchain script: adding sim url path	julius	5074d 12h	/
367	Fixup 1.0 release script	julius	5074d 12h	/
366	Version 1.0 toolchain script commit	julius	5074d 12h	/
365	Linux-2.6.34 patch update with updated USB ohs900 host	julius	5077d 06h	/
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5086d 05h	/
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5086d 15h	/