URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 465

Rev	Log message	Author	Age	Path
445	gdbserver update to use kernel port ptrace register definitions.	julius	5006d 16h	/
444	Changes to ABI handling of varargs.	jeremybennett	5007d 01h	/
443	Work in progress on more efficient Ethernet.	jeremybennett	5007d 05h	/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	5007d 19h	/
441	Changes for gdbserver.	jeremybennett	5008d 01h	/
440	Updated documentation to describe new Ethernet usage.	jeremybennett	5008d 20h	/
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	5011d 01h	/
438	Fix to newlib header and library locations.	jeremybennett	5014d 01h	/
437	Or1ksim - ethernet peripheral update, working much better.	julius	5016d 15h	/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	5017d 15h	/