URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 497

Rev	Log message	Author	Age	Path
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4903d 06h	/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4903d 23h	/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	4904d 01h	/
474	uC/OS-II port linker flags updated.	julius	4904d 07h	/
473	Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux.	jeremybennett	4905d 02h	/
472	Various changes which improve the quality of the tracing.	jeremybennett	4905d 03h	/
471	Adding ucos-ii port.	julius	4907d 06h	/
470	ORPSoC OR1200 crt0 updates.	julius	4908d 01h	/
469	newlib update - added zeroing of r0 to crt0.S	julius	4909d 02h	/
468	ORPSoC update: Added USER_ELF and USER_VMEM options to reference design simulation scripts. Changed use of absolute BOARD_PATH variable to simply BOARD relative to board path ML501's board.h bootrom default now boot from SPI	julius	4909d 03h	/