URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 67

Rev	Log message	Author	Age	Path
47	debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions	julius	5397d 00h	/
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5403d 00h	/
45	Orpsoc eth test fix and script error message update	julius	5410d 00h	/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5438d 23h	/
43	Couple of fixes to ORPSoC, new linux patch version in toolchain script	julius	5462d 20h	/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5478d 17h	/
41	Update to or1k top	julius	5481d 19h	/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5483d 00h	/
39	Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update	julius	5487d 00h	/
38	Adding binutils, gcc, uClibc patched source and patches	julius	5497d 00h	/