URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] - Rev 498

Rev	Log message	Author	Age	Path
478	ORPSoC update - ml501 or1200 cache configuration set to maximum, some cleanups.	julius	4926d 18h	/
477	ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts. Changed cache sizes of both instruction and data cache of reference design to 4kB each.	julius	4927d 02h	/
476	ORPSoC updates. Added 16kB cache options to OR1200, now as default on reference design. Cleaned up simulation Makefile more.	julius	4927d 19h	/
475	ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0.	julius	4927d 22h	/
474	uC/OS-II port linker flags updated.	julius	4928d 04h	/
473	Fix typos in tool chain build script. Add build script for BusyBox/uClibc/Linux. Delete obsolete scripts, improve board description for test, add -pthread flag to GCC for Linux.	jeremybennett	4928d 22h	/
472	Various changes which improve the quality of the tracing.	jeremybennett	4928d 23h	/
471	Adding ucos-ii port.	julius	4931d 02h	/
470	ORPSoC OR1200 crt0 updates.	julius	4931d 22h	/
469	newlib update - added zeroing of r0 to crt0.S	julius	4932d 23h	/