URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] - Rev 459

Rev	Log message	Author	Age	Path
439	ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC FIFO synthesis issues with Xilinx XST Multiply/divide tests for to run on target. Added third interface to ram_wb module, changed reference design RAM to ram_wb wrapper. Updated verilog and system C monitor modules accordingly. Added ability to use ram_wb as internal memory on ML501 design. Fixed ethernet MAC tests for ML501.	julius	4951d 00h	/
438	Fix to newlib header and library locations.	jeremybennett	4954d 00h	/
437	Or1ksim - ethernet peripheral update, working much better.	julius	4956d 14h	/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	4957d 14h	/
435	ORPSoC updates OR1200 multiply/MAC/division unit update with serial multiply and divide options. Full divide not synthesizable yet. New software tests of multiply and divide functionality.	julius	4957d 15h	/
434	Work in progress with new Ethernet TUN/TAP interface.	jeremybennett	4960d 20h	/
433	New single program interrupt test programs.	jeremybennett	4961d 23h	/
432	Updates to handle interrupts correctly.	jeremybennett	4962d 00h	/
431	Updated and move OR1200 supplementary manual. or_debug_proxy GDB RSP interface fix. ORPSoC S/W and makefile updates.	julius	4963d 22h	/
430	or1ksim - clarifying interrupt behavior in code and documentation.	julius	4964d 20h	/