URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 82

Rev	Log message	Author	Age	Path
62	Added BIST signals for RAMs.	mihad	7910d 03h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7918d 03h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7918d 03h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7918d 05h	/
58	Removed all logic from asynchronous reset network	mihad	7923d 05h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7923d 11h	/
56	Number of state bits define was removed	mihad	7924d 02h	/
55	Changed state machine encoding to true one-hot	mihad	7924d 02h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7957d 04h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7957d 07h	/