URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 87

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	7923d 07h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7926d 17h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7929d 15h	/
64	The testcase I just added in previous revision repaired	mihad	7929d 17h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 19h	/
62	Added BIST signals for RAMs.	mihad	7932d 12h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7940d 12h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7940d 12h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7940d 13h	/
58	Removed all logic from asynchronous reset network	mihad	7945d 14h	/