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Rev Log message Author Age Path
69 Changed BIST signal names etc.. mihad 7930d 18h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7934d 03h /
67 Changed BIST signals for RAMs. tadejm 7934d 08h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7937d 19h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7940d 17h /
64 The testcase I just added in previous revision repaired mihad 7940d 19h /
63 Added additional testcase and changed rst name in BIST to trst mihad 7940d 21h /
62 Added BIST signals for RAMs. mihad 7943d 14h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7951d 14h /
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7951d 14h /

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