URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 124

Rev	Log message	Author	Age	Path
104	- Added missing signal dmem_data_in.	cwalter	6391d 02h	/
103	- Added simulation for memory to behavioral. - Added empty mif file for memory.	cwalter	6391d 02h	/
102	changed data pitch	ustadler	6393d 07h	/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6393d 08h	/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6393d 08h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6393d 08h	/
98	- Applied indenting tool.	cwalter	6393d 08h	/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6393d 09h	/
96	- SR register is now computed in ALU stage.	cwalter	6393d 09h	/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6393d 09h	/