URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 128

Rev	Log message	Author	Age	Path
108	no message	cwalter	6413d 02h	/
107	- Added new example for memory testing.	cwalter	6413d 02h	/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6413d 02h	/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6413d 02h	/
104	- Added missing signal dmem_data_in.	cwalter	6413d 03h	/
103	- Added simulation for memory to behavioral. - Added empty mif file for memory.	cwalter	6413d 03h	/
102	changed data pitch	ustadler	6415d 08h	/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6415d 08h	/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6415d 09h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6415d 09h	/