URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 69

Rev	Log message	Author	Age	Path
49	data can be ead asynchronous, data is written with the rising edge of the clk	ustadler	6412d 15h	/
48	- Added ModelSim files.	cwalter	6412d 17h	/
47	- Added GNU assembler patch.	cwalter	6412d 17h	/
46	- Added constant for RESET_VECTOR.	cwalter	6412d 19h	/
45	- Fixed latch for pc_next.	cwalter	6413d 11h	/
44	- Added another version of a register file which is a bit simplier.	cwalter	6413d 11h	/
43	Correct implementation of necessary unlocking signals that are conncted to register locking unit.	jlechner	6413d 11h	/
42	Modified input signals for register locking (testbench modifications): Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6413d 11h	/
41	Modified input signals for register locking: Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).	jlechner	6413d 11h	/
40	- Added seperate memory output vector to MEM_WB_REGISTER. - Added status register to MEM_WB_REGISTER.	jlechner	6413d 11h	/