URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] - Rev 60

Rev	Log message	Author	Age	Path
40	First version of synthesis script for Xilinx ISE XST	fafa1971	6302d 17h	/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6302d 17h	/
38	Changed to compile (for now) the boot code.	fafa1971	6306d 16h	/
37	Memory image coming from the new boot.s	fafa1971	6306d 16h	/
36	Working boot code!!!	fafa1971	6306d 16h	/
35	Fixed Assembly comments ("//" had to become "!!").	fafa1971	6306d 17h	/
34	This file is useless.	fafa1971	6316d 01h	/
33	Added inclusion of defines.h in boot.s	fafa1971	6316d 16h	/
32	First version of cutdown boot code for SPARC V9.	fafa1971	6316d 17h	/
31	Removed list of formerly dirty signals, to improve waveforms readability.	fafa1971	6316d 18h	/